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PI6C104
Spread Spectrum Clock Synthesizer for Desktop Pentium II
Features
* Up to 112 MHz operation * Spread Spectrum Modulation for CPUCLK, and PCICLK * Two copies of CPU clock with VDD of 2.5V 5% * Seven copies of PCI clock, (synchronous with CPU clock) 3.3V * One copy of Ref. clock @ 14.31818MHz (3.3VTTL) * 48MHz USB Clock, 24MHz Super I/O clock * I2C Serial Configuration Interface * Low cost 14.31818MHz crystal oscillator input * Power management control * Isolated core VDD, VSS pins for noise reduction * 28-pin SSOP (H) and SOIC package (S)
Description
The PI6C104 is a high-speed low-noise clock generator designed to work with the PI6C18X family of clock buffer to meet all clock needs for Desktop Intel Architecture platforms. CPU and chipset clock frequencies from 66.6 MHz to 112 MHz are supported. Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers a portion of the I/O and the core. The 2.5V is used to power the remaining outputs (CPU and APIC). 2.5V signaling follows JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is not required. An asynchronous PD# signal may be used to orderly power down (or up) the system during power on.
Block Diagram
VDDAPIC APIC
Pin Configuration
XTAL_IN XTAL_OUT VSS PCICLK_F/S1
VDDCPU 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS REF1/P14 VDD VDD2 APIC VDD2 CPUCLK0 CPUCLK1 VDD VSS SDATA SCLK S0 VSS
VDDREF XTAL_IN XTAL_OUT REF OSC REF1
PCICLK1
CPUCLK[0:1]
SEL PLL1 S[0..2] Div VDDPCI0,1 6
PCICLK2 PCICLK3
28-Pin H, S
PCICLK[1:6]
PCICLK4 VDD PCICLK5 PCICLK6/PD# VDD 48M/MODE 24M/REF/S2
SDATA SCLOCK
I2C PCICLK_F
VDDP2 PLL2 48MHz
MUX PI4
24MHz/REF
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PI6C104 Spread Spectrum Clock Synthesizer for Desktop Pentium II
Pin Description
Pin 1 2 Signal Name XTAL_IN XTAL_O UT PCICLK _F 4 S1 Type XI XO O I+PU Qty. 1 1 1 14.318 MHz crystal input 14.318 MHz crystal input Free running PCI clock output. Frequency Select bit 1 During power up this pin is S1 input, PCICLK _F output otherwise 5,6,7,8,10 PCICLK [1:5] PCICLK 6 11 PD# O O I+PU 1 5 PCI clock outputs. PCI clock outputs. Active low Power Down input. PCI and CPU clocks are disabled when PD# is low, except for PCICLK _F This pin is set by MO DE (pin 13). MO DE = 0: PD# input, MO DE = 1: PCICLK 6 output 48M 13 MO DE O I+PU 1 48 MHz output MO DE determines the definition of pin 11, 0=PD# input, 1=PCICLK 6 output This is a an input, sampled during power up. Becomes 48 MHz output after power up 24M REF 14 S2 O O I+PU 1 24 MHz output Buffered Reference output. Frequency Select bit 2. During power up this pin is S2 input, output otherwise. P14 (pin 27) mode selects: 0 = REF, 1 = 24 MHz 16 17 18 21,22 24 S0 SCLK SDATA CPUCLK [0:1] APIC REF1 27 P14 I+PU I+PU IO +PU O O O 1 1 1 1 2 1 1 1 Frequency Select bit 0 Serial Clock for I2C interface Serial Data for I2C interface CPU clock output Buffered Crystal output. Buffered Crystal output. Pin 14 mode select, 0 = REF1, 1 = 24 MHz During power up this pin is P14 input, REF1 output otherwise. 9,12,20,26 23,25 3,15,19,28 VDD VDD2 VSS 4 2 4 Power supply for PCI, Core, REF, PLL. 3.3V Power supply for APIC & CPU clocks. 2.5V Grounds D e s cription
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PI6C104 Spread Spectrum Clock Synthesizer for Desktop Pentium II
Clock Enable Configuration
PD# 0 1 CPUCLK[0:1] PCICLK[1:5] PCICLK_F Othe r Clocks low Running low Running Running Running Running Running Crys tal Running Running VCO's Running Running
PI6C104 I2C Address Assignment 0D2H
A7
1
A6
1
A5
0
A4
1
A3
0
A2
0
A1
1
A0
0
Fre que ncy Table S0 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S2 0 1 0 1 0 1 0 1 CPU 75 66.8 66.6 66.8 112 83.3 100 100 PCI 30 33.4 33.3 33.4 37.3 33.3 33.3 33.3
2-Wire I2C Control
The I2C interface permits individual enable/disable of each clock output and test mode enable. The PI6C104 is a slave receiver device. It can not be read back. Sub addressing is not supported. All preceding bytes must be sent in order to change one of the control bytes. Every byte put on the SDATA line must be 8-bits long (MSB first), followed by an acknowledge bit generated by the receiving device. During normal data transfers SDATA changes only when SCLK is LOW. Exceptions: A HIGH to LOW transition on SDATA while SCLK is HIGH indicates a start condition. A LOW to HIGH transition on SDATA while SCLK is HIGH is a stop condition and indicates the end of a data transfer cycle. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW = write to addressed device). If the devices own address is detected, PI6C104 generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. Following acknowledgement of the address byte (D2), two more bytes must be sent: 1. Command Code byte, and 2. Byte Count byte. Although the data bits on these two bytes are dont care, they must be sent and acknowledged.
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PI6C104 Spread Spectrum Clock Synthesizer for Desktop Pentium II
Byte 3 : Frequency, Spread Spectrum
Bit # 7 6 5 4 3 2 1 0 0 Pup Pin # ~ ~ ~ ~ ~ ~ ~ ~ Name RSVD S0 S1 S2 S FS RSVD Reserved Frequency Select Bit 0 Frequency Select Bit 1 Frequency Select Bit 2 0 = Hardware Frequency Select 1 = Software Frequency Select (12C reg.) Reserved D e s cription
MO DE1 Mode Bit 1 MO DE0 Mode Bit 0 M1 0 0 1 1 M0 0 1 0 1 Spread Spectrum O ff Test Mode Spread Spectrum O n Hi- Z
Byte 4 : Clock Controls (1 = Enabled, 0 = Disabled)
Bit # 7 6 5 4 3 2 1 0 1 0 1 0 Pup Pin # ~ ~ ~ ~ ~ 21 ~ 22 CPU1EN RSVD CPU0EN CPUCLK1 Enable, Default is Enable Reserved CPUCLK0 Enable, Default is Enable RSVD Reserved Name De s cription
Byte 5 : PCI Clock Control (1 = Enabled, 0 = Disabled)
Bit # 7 6 5 4 3 2 1 0 1 Pup 1 0 1 0 Pin # 4 11 10 ~ 8 7 6 5 Name D e s cription PCIFEN PCI_F Enable, Default is Enable PCI6EN PCI6 Enable, Default is Enable PCI5EN PCI5 Enable, Default is Enable ~ Reserved PCI4EN PCI4 Enable, Default is Enable PCI3EN PCI3 Enable, Default is Enable PCI2EN PCI2 Enable, Default is Enable PCI1EN PCI1 Enable, Default is Enable
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PI6C104 Spread Spectrum Clock Synthesizer for Desktop Pentium II
Byte 6 : REF Clock Control (1 = Enabled, 0 = Disabled)
Bit # 7 6 5 4 2 1 0 1 0 Pup Pin # ~ ~ 24 ~ ~ 26 26 Name RSVD RSVD RSVD RSVD RFEN0 Reserved Reserved Reserved Reserved REF1 High drive Enable 0 RFEN1 0 Low Drive Normal Drive, Default High Drive 0 1 1 RFEN0 0 1 0 1
Note: Outputs are disabled @ low state
De s cription
APICEN APIC Enable, Default is Enable
RFEN1 REF1 High drive Enable 1
Table 1: Byte 3 Frequency and Spread Spectrum Table
Bit3 SFS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit1 SSEN 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit6 S0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit5 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit4 S2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU(M Hz) 75 66.8 66.6 66.8 112 83.3 100 100 75 66.8 66.6 66.8 112 83.3 100 100 PCI(M Hz) 30 33.4 33.3 33.4 37.3 33.3 33.3 33.3 30 33.4 37.3 33.4 37.3 33.3 33.3 33.3 Spre ad (%) O FF O FF O FF O FF O FF O FF O FF O FF - 0.5~+0.5 - 0.9~+0.9 - 1.0~+0.0 - 0.5~+0.5 - 0.5~+0.5 - 0.5~+0.5 - 1~+0.0 - 0.5~+0.0
Notes: Bit 3 = Enable Software Frequency Select Bit 1 = Enable Software Frequency Select Bit 6 = Frequency Select 0 Bit 5 = Frequency Select 1 Bit 4 = Frequency Select 0
Byte 0: Test Mode Table
Bit 1 0 0 1 1 Bit 0 0 1 0 1 CPU table 1 Xin/2 table 1 Hi- Z PCI table 1 Xin/6 table 1 Hi- Z 48M 48MHz Xin/2 48MHz Hi- Z 24M 24 MHz/Ref Xin/4 24 MHz/Ref Hi- Z
238
REF/APIC 14.318MHz Xin 14.318MHz Hi- Z
M ode Normal Test SSC Tri- state
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PI6C104 Spread Spectrum Clock Synthesizer for Desktop Pentium II
Power Management Timing
When MODE = 0, the device supports power management and pin 11 is input PD#. When MODE = 1, this function is not available). A particular output is enabled only when both the I2C serial interface and this pin indicate that it should be enabled. The clocks may be disabled according to the following table in order to reduce the power consumption. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped. The CPU and PCI clocks transition between running and stopped by waiting for one positive edge on PCI_F followed by a negative edge on the clock of interest, after which high levels of the outputs are either enabled or disabled. See Figure 1 below.
PCI_F PD# PCI (1:5) CPU (0:1) B A
A: Represents one PCI clock wait cycle B: Represents one CPU clock wait cycle
Figure 1. PD# Timing Diagram Note: 1. Please note that all clocks can also be individually (asynchronously) enabled or stopped via the 2-wire I2C control interface. In this case all clocks are stopped in the low state.
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PI6C104 Spread Spectrum Clock Synthesizer for Desktop Pentium II
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..............................................................65C to +150C Ambient Temperature with Power Applied ............................... 0C to +70C 3.3V Supply Voltage to Ground Potential .................................. 0.5V to +4.6V 2.5V Supply Voltage to Ground Potential .................................. 0.5V to +3.6V DC Input Voltage ....................................................................... 0.5V to +4.6V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics (VDD = +3.3V 5%, VDD2 = +2.5V 5%, TA = 0C to +70C)
Parame te rs IDD2 IDD2 IDD2 IDD IDD IDD 3.3V Current 2.5V Current D e s cription Te s t Conditions VDD2 = 2.625V, PD# = 0 CLO AD = Max. VDD2 = 2.625V @ 66.66MHz CLO AD = Max. VDD2 = 2.625V @ 100MHz CLO AD = Max. VDD = 3.465V, PD# = 0 CLO AD = Max. VDD = 3.465V @ 66.66MHz CLO AD = Max. VDD = 3.465V @ 100MHz CLO AD = Max. M in. Typ. M ax. 100 72 mA 100 500 170 mA 170 mA Units mA
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PI6C104 Spread Spectrum Clock Synthesizer for Desktop Pentium II
DC Operating Specifications
Symbol Parame te rs Conditions M in. M ax. Units Input Voltage , VDD = 3.3V 5% VIH3 VIL3 IIL Input high voltage Input low voltage Input leakage current 0 < VIN < VDDCORE VDDCORE 2.0 VSS - 0.3 -5 VDDCORE +0.3 0.8 +5 V mA
Output Voltage , VDD2 = 2.5V 5% VOH VOL Output high voltage Output low voltage IOH = - 1mA IOL = 1mA 2.0 0.4 V
Output Voltage , VDD = 3.3V 5% VOH VOL Output high voltage Output low voltage IOH = - 1mA IOL = 1mA 2.4 0.4 V
Output Voltage , VDD = 3.3V 5% VPOH VPOL PCI Bus output high voltage PCI Bus output low voltage IOH = - 1mA IOL = 1mA 2.4 0.55 V
CIN CXTAL COUT LPIN TA
Input pin capacitance Xtal pins capacitance Output pin capacitance Pin Inductance Ambient Temperature No airflow 0 13.5 18.0
5 22.5 6 7 70 nH C pF
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PI6C104 Spread Spectrum Clock Synthesizer for Desktop Pentium II
Buffer Specifications
VDD Range (V) 2.375 - 2.625 3.135 - 3.465 Impe dance (W) 13.5 - 45 12 - 55 Buffe r Type Type 1 Type 5
Type 1: 2.5V Clock Buffers
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRH tFH Parame te rs Pull- up current Pull- up current Pull- down current Pull- down current 2.5V Type 1 output rise edge rate 2.5V Type 1 output fall edge rate Conditions VOUT = 1.0V VOUT = 2.375V VOUT = 1.2V VOUT = 0.3V 2.5V 5% @ 0.4V- 2.0V 2.5V 5% @ 2.0V- 0.4V 1 1 27 30 4 4 V/ns M in. - 27 - 27 mA Typ. M ax. Units
Type 5: 3.3V Clock Buffers
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRH tFH Parame te rs Pull- up current Pull- up current Pull- down current Pull- down current 3.3V Type 5 output rise edge rate 3.3V Type 5 output fall edge rate Conditions VOUT = 1.0V VOUT = 3.135V VOUT = 1.95V VOUT = 0.4V 3.3V 5% @ 0.4V- 2.4V 3.3V 5% @ 2.4V- 0.4V 1 1 30 38 4 4 V/ns M in. - 33 - 33 mA Typ. M ax. Units
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PI6C104 Spread Spectrum Clock Synthesizer for Desktop Pentium II
AC Timing
Figure 1. Hos t Clock to PCI CLK Offs e t tHKP (2.5V) tHKH (2.5V) tHKL (2.5V) tHRISE (2.5V) tHFALL (2.5V) tJITTER (2.5V) Duty Cycle (2.5V) tHSKW (2.5V) tPZL, tPZH tPLZ, tPHZ tHSTB tPKP tPKPS
tPKH
Parame te rs Host CLK period Host CLK high time Host CLK low time Host CLK rise time Host CLK fall time Host CLK Jitter Measured at 1.25V Host Bus CLK Skew Output enable delay Output disable delay Host CLK Stabilization from power- up PCI CLK period PCI CLK period stability PCI CLK high time PCI CLK low time PCI Bus CLK Skew Host to PCI Clock Offset PCI CLK Stabilization from power- up
66 M Hz M in. 15.0 5.2 5.0 0.4 0.4 1.6 1.6 250 45 55 175 1.0 1.0 8.0 8.0 3 30.0 500 12.0 12.0 500 1.5 4.0 3 M ax. 15.5
100 M Hz M in. 10.0 3.0 2.8 0.4 0.4 1.6 1.6 250 45 55 175 1.0 1.0 8.0 8.0 3 30.0 500 12.0 12.0 500 1.5 4.0 3 M ax. 10.5
Units
ns
ps % ps ns ms ns ps ns ps ns ms
tPKL tPSKW tHPOFFSET tPSTB
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PI6C104 Spread Spectrum Clock Synthesizer for Desktop Pentium II
2.5V
1.25V Host CLK tHSKW
1.25V VSS 2.5V
1.25V Host CLK tHPOFFSET
1.25V VSS tHPOFFSET 3.3V
1.5V PCI CLK tPSKW
1.5V VSS 3.3V 1.5V
PCI CLK
VSS
Figure 1. Host Clock and PCI CLK Timing
Output Buffer Test Point
Test Load
tHKP
Duty Cycle
tHKH
2.5V 2.0 Clocking 1.25 Interface 0.4
tHKL tHrise tHfall tPKP tPKH
3.3V Clocking Interface (TTL)
2.4 1.5 0.4 tPKL tPrise tPfall
Figure 2. Clock Output Waveforms
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PI6C104 Spread Spectrum Clock Synthesizer for Desktop Pentium II
PCB Layout Suggestion
FB1
1 2
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS C6 VDD VDD C5 C4 VDD 22F C7 FB2 VCC
VCC C1
VSS
3 4 5
22F
6 7 8 9 10 C2 VDD 11 12 13 14
C3 VDD VSS
Via to VDD Plane Via to GND Plane VSS Void in Power Plane
Note: This is only a suggested layout. There may be alternate solutions depending on actual PCB design and layout. As a general rule, C2-C6 should be placed as close as possible to their respective VDD.
Recommended capacitor values: C2-C6 ............... 0.1uF, ceramic C1, C7 ............. 22uF
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PI6C104 Spread Spectrum Clock Synthesizer for Desktop Pentium II
Minimum and Maximum Expected Capacitive Loads
Clock CPU Clocks (HCLK ) PCI Clocks (PCLK ) REF, 48MHz M in. Load 10 30 10 M ax. Load 20 30 20 pF Units Note s 1 device load, possible 2 loads Meets PCI 2.1 requirements 1 device load
Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer. 2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500 resistor in parallel.
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10pF. RS Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values. 2. Minimize the number of vias of the clock traces. 3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2). 4. Position clock signals away from signals that go to any cables or any external connectors.
21$+"
2 CPUCLK CL 7 PCICLK CL 2 REF CL Rs APIC Ct 1 Device load Rs 1 Device load Rs Meets PCI2.1 Req. Rs 1 Device load
Design Guidelines to Reduce EMI
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28-Pin SOIC Package Data
28
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C104 Spread Spectrum Clock Synthesizer for Desktop Pentium II
28-Pin SSOP Package Data
28
.197 .220
5.00 5.60
1
.390 .413 9.90 10.50 0.55 .078 2.0 .291 SEATING PLANE .322 7.40 8.20 0.95 Max .022 .037 .004 .009 0.09 0.25
.0256 BSC 0.65
.0098 Max. 0.25
.002 0.050
Min
X.XX X.XX
DENOTES DIMENSIONS IN MILLIMETERS
.2914 .2992
7.40 7.60
1 .6969 17.70 .7125 18.10 0-8 .021 0.533 .031 0.787 .0926 .1043 2.35 2.65 SEATING PLANE
.010 .029
0.254 x 45 0.737
.0091 .0125 0.41 .016 1.27 .050 .394 .419 10.00 10.65
0.23 0.32
REF
.050 BSC 1.27
.013 .020 0.33 0.51
.0040 .0118
0.10 0.30
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
Ordering Information
P/N PI6C104H PI6C104S D e s cription 28- pin SSO P Package 28- pin SO IC Package
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
247
PS8164B 03/15/99

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Price & Availability of PI6C104

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